External message passing method and apparatus

ABSTRACT

An apparatus which uses channel counters in combination with channel count read instructions as a means of providing information that data in a given channel is valid or has not been previously read. The counter may also, in the situation of the channel being defined as blocking, be used to prevent the unintentional overwriting of data in a register used by the channel or, alternatively, prevent further communications with the device assigned to that channel when a given count occurs. Intelligent external devices may also use channel count read instructions sent to the counting mechanism for reading from and writing to the channel.

TECHNICAL FIELD

[0001] The invention relates to a method of and apparatus fortransmitting messages to and/or receiving messages from external devicesby a PU (processing unit).

BACKGROUND

[0002] Normally, in the prior art, when a CPU or other PU (central orother processing unit) is waiting upon some event external to theprogram, the operating system or an active program will run a poll loopwhere it will keep reading an event register, utilized by the PU inconnection with the program, until the event that it is waiting uponoccurs. While the program is operating the PU in polling the eventregister, the PU is not doing useful work. Typical modern processorsoften use virtual memory and the memory mapping of external devices forthis communication. On the other hand, some processors, especially in amultiprocessor environment, only have access to local memory and not tovirtual memory. Local memory is finite and, in typical multiprocessorconfigurations, no memory outside of this local memory can be accessedby load and store operations. Thus, the use of local memory for other PUfunctions is limited while awaiting response from an external device. Ifa PU is simultaneously awaiting communication responses from severaldevices, the available memory for other functions is even furtherlimited.

[0003] Memory may also be used to keep track of whether or not there isvalid data in an incoming or outgoing register. Valid data is data thathas been placed in the register for use by a receiving device but hasnot yet been accessed by the receiving device.

[0004] It would thus be desirable to provide a mechanism forcommunicating with one or more external devices without burdening thelocal or even the virtual memory of a PU.

[0005] It would further be desirable to keep track of valid data withoutburdening receiving device memory.

SUMMARY OF THE INVENTION

[0006] The present invention comprises using a PU control mechanismdesignated as a read or write channel register and associated channelmessage counting logic for maintaining communication with externaldevices.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] For a more complete understanding of the present invention, andits advantages, reference will now be made in the following DetailedDescription to the accompanying drawings, in which:

[0008]FIG. 1 is a generalized block diagram of a computer includingexternal devices supplying inputs thereto and receiving communicationstherefrom;

[0009]FIG. 2 shows the PU in more detail for the portions relevant thepresent invention; and

[0010]FIGS. 3A and 3B show a flow diagram of the process occurring withrespect to reads and writes in FIG. 2.

DETAILED DESCRIPTION

[0011] In the remainder of this description, a processing unit (PU) maybe a sole processor of computations in a device. In such a situation,the PU is typically referred to as a CPU (central processing unit). Theprocessing unit may also be one of many processing units that share thecomputational load according to some methodology or algorithm developedfor a given multiprocessor computational device. Where there are morethan one processing units on a single chip, these PUs are sometimesreferred to as SPUs (special or synergistic processing units). For theremainder of this discussion all references to processors shall use theterm PU whether the PU is the sole computational element in the deviceor whether the PU is sharing the computational with other PUs.

[0012] In FIG. 1, a PU 10 is illustrated connected to a variety ofcomponents, such as memory 12, hard disk storage 14 and a monitor 16. Inaddition, there are shown various components, such as a printer 18, akeyboard 20, a cursor controlling device like a mouse or trackball 22,and a modem 24 that supply responses to the PU in accordance withevents, such as a key being pressed on the keyboard 20, the printer 18running out of paper or a button being pressed on the device 22. Thememory 12 may include local cache memory as well as RAM (random accessmemory) and other memory, such as permanent storage memory and virtualmemory. This memory 12 may further include a memory flow controller.

[0013] In FIG. 2, a block 30 represents external device instructionissue and control logic of a processor. A block 32 represents data flowto and from a processor. As is known, a processor may simultaneously bein communication with many different external devices. In the presentprocessor, the communication is accomplished via a channel register.Each channel operates in one direction only, and is called either a ReadChannel or a Write Channel, according to the operation that can beperformed on the channel by the PU. A block 34 represents the channellogic for one set of channels for a single external device asrepresented by a block 35. Within block 34 there is shown a read channelcounter 36, a read register 38, a write channel counter 40, a writeregister 42, a MUX (multiplexer) 44 and a MUX 46. Channel instructionsare delivered from the PU 30 on a bus 48 to the read and write counters36 and 40 as well as to a gate input of the MUXs 44 and 46. Theseinstructions are also supplied on a lead further designated as 50 to theappropriate external device such as 35. A data IN lead 52 provides datafrom the external device 35 to read register 38. A channel count INsignal is supplied from the external device 35 on a lead 54 to counter36 signifying that data has been input to the register and operating toalter the count in counter 36 by one value or digit. The data beingoutput to the external device from write register 42 is supplied on alead designated as 56. A channel acknowledgement signal is returned fromexternal device 35 on a lead 58 to write channel counter 40 when theexternal device has completed satisfactory reception of the data andoperates to alter the count in counter 40 by one value unit or digit. Ina preferred embodiment of the invention, a signal on bus 48 willdecrement the appropriate read or write counter while a signal on eitherlead 54 or 58 will increment the appropriate read or write counter. Asshown, the count of both of the counters 36 and 40 is supplied throughthe MUX 44 on a lead 60 to logic block 30. Channel write data issupplied from data flow block 32 on a lead 62 to the write register 42.Outputs from blocks 36, 38 and 40 are returned to data flow block 32 ona bus 64. Non channel instructions are communicated between blocks 30and 32 via a bus 66.

[0014] In the drawings of FIGS. 3A and 3B, the issuance of a channelread or write instruction will cause a determination in decision block76 as to whether or not the channel specified is one where a controlmechanism, as set forth above, has been implemented. If not, adetermination is made in block 78 as to whether channel errors logic isenabled. If so, the processor is stopped as set forth in a block 80. Ifnot, in a block 82, a determination is made as to whether the command isa read or a write. If it is a write, nothing further is done for thatcommand as set forth in a block 84. On the other hand, if thenon-implemented command is a read, zeros are returned to the dataprocessor data flow as indicated in block 86. In either case, theprocess returns to a status of awaiting the next read or writeinstruction. In the preferred embodiment shown, all valid readinstructions must return a value. As defined herein, channel readinstructions to a non-implemented channel return a value of all zeroes.

[0015] It may be noted that for a particular implementation, not allchannels have to be defined. Each channel will have a unique numericalidentifier. In a preferred embodiment, this channel identifier rangedfrom 0 to 127. However, since not all channels need to be defined, notall identifiers are used. Thus, if there is an instruction to anundefined channel, then the process goes down the above-referencednon-implemented path. It may be desired, in some implementations, thatchannel read or write commands to non-implemented channels be consideredan illegal operation. The further action may possibly be to force theprocessor to stop, as shown in the previously mentioned block 80.

[0016] If, in block 76, it is determined that the channel specified hasbeen implemented, a check is made, in block 88, to see if the specifiedchannel is a blocking channel. If not, the process continues to block 90where the count for that channel is decremented but not allowed to beless than zero. If the channel is determined to be blocking, a check ismade in a block 92 if the count for that channel is greater than zero.If so, the process returns to block 90. If the count is already at zero,as determined in block 92, further external inputs related to thischannel are stalled until the PU has a chance to read data from theregister and thus change the count from zero. Thus the loop of blocks 94and 95 is periodically processed until there is a change in the countfor this channel. Once the count is changed, the process continues fromblock 95 to block 90. The next step, from block 90, is to block 96,where it is determined if the channel is active or passive. If passive,a decision block 98 checks to see if the command is a write or readinstruction. If it is a write instruction, the data is stored locallyfor external read as shown in a block 100. If it is a read instruction,the process continues to a block 102 where the data is returned to thePU block 32 of FIG. 2.

[0017] It may be noted that, in the situation of a passive channel, thePU is dependent upon an external process to complete the operation. Asan example, a read channel may be dependant on an external device toload data. On the other hand, in an active channel, the PU activelycompletes the operation of executing a read or write operation. Anexample of this type of operation is when the connected hardware makesan external request for data from an active read channel.

[0018] When it is determined, in block 96, that the channel is an activechannel, a decision block 104 checks to see if the command is a read orwrite command. If the command is to write, the write data is completedas shown in a block 106. If the command is read, a read request is sentto the appropriate external device as set forth in a block 108. Input ofthe requested data is awaited as stated in block 110. Periodically, adetermination is made, as shown in a block 112, as to whether or not theread data has been received. If not, the action returns to block 110until the time for the next check occurs. When the data is received, theprocess is completed in previously mentioned block 102.

[0019] From the above, it will be apparent that each channel is accessedusing a specific channel read or write instruction where the channelnumber is specified in the instruction. Each channel has a countspecified with it. This count is read using a read channel countinstruction where the channel of interest is specified in theinstruction. Channel commands are not speculative and cannot beprocessed out of order at the external interface. The channelarchitecture does not require that devices external to the PU processthe channel commands in order, but may do so depending on the processorand external device implementation. The value in this count registerkeeps track of the number of accesses to this register versus the numberof external acknowledgments that have occurred to this register.

[0020] In operation, the manner of changing of the channel count viaaccesses through the external interface(s) is based on implementation.In the preferred embodiment, the count is incremented by one for eachsuccessful data transfer to or from a register. For each channel, PUaccess can be defined as a read or write channel. Further, in thepreferred embodiment, a ZERO count is used to stall further operationswhen the channel is defined or implemented as a “blocking” channel. Whena channel register is defined to have a queue depth of ONE, a ZERO countmay be used to indicate that the data in that channel is not valid. Thechannel can also be defined to stall PU operations on a read or writechannel command, on that command, if the count is zero until such timeas the count is no longer zero.

[0021] In the preferred embodiment, the counter value is decremented forevery PU initiated read or write channel command and is incremented foreach external initiated read or write (with or without data) access. Inother words, the counter maintains an indication of inputs versusoutputs. Thus, a value or count of zero indicates that, for writes, nomore external write slots are available. On the other hand, a countvalue of zero for reads indicates that there is no valid data. When thecount is zero, if an additional PU read or write channel command isissued, and the channel is defined as non-blocking, then the count willremain at zero and data in the register is lost. As implemented in thepreferred embodiment, the previously most recent data in that registeris lost. If the count is at maximum value for the number of bits of thatchannel register implementation and there occurs an additionaltransaction that would cause the count to increment out of range, thenthe count will stay at that maximum value.

[0022] The method of initializing the count value is implementationdependant, and one method is initialization through the externalinterface. This count can be used for flow control for a write queue.The count can be preset to the depth of the external queue. A value ofzero in the count register means that there is no more space in thisexternal queue. For an external queue depth of one, the count should bepreset to one. When the PU writes to this channel, the count goes tozero. When the external device reads from this channel, the count isincremented to one, thereby indicating that the channel is ready foranother write operation. As mentioned above, for reads of the channelregisters, this allows the count to indicate valid data. If the countregister is preset to zero, this indicates that the data is not valid.When the external device writes to this channel, the count increments toone, indicating the data is valid for SPU reads. When the PU reads fromthis channel, the count decrements back to zero, indicating that anotherexternal write can occur.

[0023] In a preferred embodiment of the invention, computer code channelcount read instructions are sent to the counter to ascertain the countfor both the read and write channels. When the external device is anintelligent device, such as another computer in a multiprocessorenvironment, the external device may also send channel count readinstructions to the counter to ascertain the count. In this manner, theexternal device may determine when the channel contains unread data ineither the read or write channel and/or when it is appropriate to sendadditional data to the processor containing the read channel.

[0024] In usage with this invention, the read and write channels may beeither non-accumulating or accumulating. Accumulating channels arechannels that accumulate multiple writes, that is, incoming data islogically added to data already contained in a register or other storagemeans, until the channel is read. Upon reading the channel, theaccumulating register is reset, typically to zero, and the channelbegins accumulating again. This action can be for both read or writechannels. Further, accumulating channels can be blocking ornon-blocking. Typically, accumulating channels will only have a countdepth of ‘1’ as opposed to non-accumulating channels may act to counteach write to that channel.

[0025] In summary, the present invention utilizes defined channels tofree up memory but still provide easily accessible information as towhen data in a register is valid or, in other words, has not beenpreviously read. This information is obtained by sending a channel countread instruction to the counting mechanism. When an intelligent externaldevice is connected to a given channel, a similar instruction may beused by the external device in sending or receiving data to or fromgiven channels. The present invention, through the use of the channelcount read instructions, also further prevents the accidentaloverwriting of data in a register when the specified channel is definedas a blocking channel.

[0026] Although the invention has been described with reference to aspecific embodiment, the description is not meant to be construed in alimiting sense. Various modifications of the disclosed embodiment, aswell as alternative embodiments of the invention, will become apparentto persons skilled in the art upon reference to the description of theinvention. It is therefore contemplated that the claims will cover anysuch modifications or embodiments that fall within the true scope andspirit of the invention.

What is claimed is:
 1. A system for use by a PU (processing unit) in communicating externally in a symmetrical multiprocessor system, comprising: PU issue and control logic means; PU data flow means interconnected to the PU issue and control logic means; PU channel logic means interconnected to the PU issue and control logic means and the PU data flow means, wherein said PU channel logic means includes: channel read data means and channel write data means interconnected between the PU data flow means and the PU channel logic means; channel and data input and output port means interconnected to the PU channel logic means; channel stall signal output means interconnected from the PU channel logic means to the PU issue command control logic means; and channel instruction means interconnecting the PU issue and control logic means to the PU channel logic means.
 2. The apparatus of claim 1, comprising in addition: means for keeping track of the number of communications pending with said specified device; and means for modifying further PU actions when the number of communications with said specified device reaches a given predetermined number.
 3. The apparatus of claim 2 wherein the means for modifying PU action operates to prevent further communication with said specified device until the number of communications with said specified device is caused to be altered.
 4. The apparatus of claim 1, comprising in addition: means for assigning a channel for communications with a given external device; means for placing communications for said given external device in a given storage means; means for tracking the number of communications, for a given one of read or write instructions, from a PU to a given external device in a given counter associated with said channel that has been assigned; means for tracking the number of communications, for said given one of read or write instructions, to the PU from the given external device to alter the count in the counter in a direction opposite from the counter movement when said instructions are sent from the PU; and means for validating data in said given storage means when the count for said channel is at a given value.
 5. The apparatus of claim 1, comprising in addition: means for maintaining a count of register inputs versus outputs; and means for retrieving data as valid when the count is other than a given predetermined value.
 6. The apparatus of claim 1, comprising in addition: means for maintaining a count of register inputs versus outputs; and means for preventing further writing of data into said register when the count reaches a given predetermined value.
 7. A method of checking to see if unread data has been returned from an external device, comprising: issuing a read channel count instruction; and comparing the count returned with a predetermined value to ascertain if a read register contains unread data.
 8. A method of ascertaining if there is previously unread data in a read channel, comprising: issuing a read channel count instruction; and retrieving data in the read channel when the count returned is a predetermined value.
 9. The method of claim 8 wherein the channel being read is an accumulating channel, comprising: retrieving all the data stored in the read channel when the channel is read; and resetting a channel counter associated with said read channel to a predetermined value each time the channel is read.
 10. A method of ascertaining the existence of data in a read channel that has not been previously read, comprising: sending a channel count read instruction to a read channel counter; and reading the data in that channel if the count returned is within a given range of counts.
 11. A method of ascertaining that an external device has not read data in a write channel, comprising: sending a channel count read instruction to a write channel counter; and writing further data to that channel only if the count returned is within a given range of counts.
 12. A computer program product for ascertaining that an external device has not read data in a write channel, the computer program product having a medium with a computer program embodied thereon, the computer program comprising: computer code for sending a channel count read instruction to a write channel counter; and computer code for writing further data to that channel only if the count returned is within a given range of counts.
 13. A computer program product for ascertaining the existence of data in a read channel that has not been previously read, the computer program product having a medium with a computer program embodied thereon, the computer program comprising: computer code for sending a channel count read instruction to a read channel counter; and computer code for reading the data in that channel if the count returned is within a given range of counts.
 14. A microprocessor, comprising: read channels; write channels; incoming data counting mechanisms for at least some of said read and write channels; and instruction processing means responding to external device generated instructions requesting a determination of the count in said data counting mechanism of at least one of said write channel and read channels having counting mechanisms.
 15. A method of sending data to an external device, comprising: sending data to a write channel via a write channel instruction; sending a channel count read instruction to a counter associated with said write channel; and ascertaining that a count indication returned is within a predetermined range of values before sending more data to said write channel.
 16. A method of receiving data from an external device, comprising: retrieving data from a read channel via a read channel instruction; sending a channel count read instruction to a counter associated with said read channel; and ascertaining that a count indication returned is within a predetermined range of values before attempting to retrieve more data from said read channel.
 17. A computer program product for sending data to an external device, the computer program product having a medium with a computer program embodied thereon, the computer program comprising: computer code for sending data to a write channel via a write channel instruction; computer code for sending a channel count read instruction to a counter associated with said write channel; and computer code for ascertaining that a count indication returned is within a predetermined range of values before sending more data to said write channel.
 18. A computer program product for receiving data from an external device, the computer program product having a medium with a computer program embodied thereon, the computer program comprising: computer code for retrieving data from a read channel via a read channel instruction; computer code for sending a channel count read instruction to a counter associated with said read channel; and computer code for ascertaining that a count indication returned is within a predetermined range of values before attempting to retrieve more data from said read channel.
 19. Apparatus for transmitting data between a PU and an external device, comprising: a data storage register; means, comprising a part of said register, operable to accumulate data received from multiple writes directed to said register; and means, comprising a part of said register, operable to transmit all data accumulated in said register in response to a single received read instruction. 